1. Field of the Invention
The present invention relates to a semiconductor memory device the data of which can be read out at high speed.
2. Description of the Prior Art
FIG. 4 is a circuit diagram showing an example of a conventional semiconductor memory device. In the figure, reference numeral 45 denotes a sense amplifier circuit. Reference numeral 46 denotes a selector circuit. Reference numeral 47 denotes a memory cell block. Reference numeral 48 denotes a bit lines grounding circuit.
In the sense amplifier circuit 45, reference letter MP1 denotes a P-channel transistor. Reference numeral 44 denotes a three-state buffer. Reference numeral 32 denotes a memory read out signal line which takes the "L" logic level at the time of reading out the data of the memory cell block 47. Reference numeral 34 denotes an input signal line of the circuit 45. Reference numeral 38 denotes an output line of the circuit 45.
In the selector circuit 46, reference letters MN5 and MN6 denote transistors which are turned on when selector signal lines 39 and 40 take the "H" logic level respectively for connecting bit lines 36 and 37 with sense amplifier circuit 45.
In the memory cell block 47, reference numerals 36 and 37 denote bit lines. Reference numerals 41-43 denote word lines which are properly selected in conformity with address signals input into the memory device and take the "H" logic level in case of being selected and the "L" logic level in case of not selected. Reference letters MN7-MN12 denote N-channel memory transistors (hereinafter simply referred to as memory transistors) which are set to have a high threshold value to the storing information of "1" or a low threshold value to the storing information of "0". Reference letters C1 and C2 denote the stray capacitance of the drain of each memory transistor, the wires of the bit lines 36 and 37, and the like.
In the bit lines grounding circuit 48, reference letters MN13 and MN14 denote N-channel transistors for grounding the bit lines 36 and 37 to fix them at the "L" logic level when the memory read out signal line 32 takes the "H" logic level, and for separating the bit lines 36 and 37 from the ground electric potential when the line 32 takes the "L" logic level.
Next, the operation thereof will be described.
FIG. 5(a) through FIG. 5(h) are timing charts showing a voltage waveform at each part of the memory device when data is read out from the memory transistor MN8, which has a low threshold value, shown in FIG. 4. FIG. 6(a) through FIG. 6(h) are timing charts showing a voltage waveform at each part of the memory device when data is read out from the memory transistor MN11, which has a high threshold value, shown in FIG. 4.
In FIG. 5(a) through FIG. 5(h) and FIG. 6(a) through FIG. 6(h), FIG. 5(a) and FIG. 6(a) show a reference clock signal 30 input into the memory device; FIG. 5(b) and FIG. 6(b) show a divided clock signal 31 obtained by dividing the frequency of the reference clock signal 30 into two; FIG. 5(c) and FIG. 6(c) show the electric potential of an address signal; FIG. 5(d) and FIG. 6(d) show the electric potential of the memory read out signal line 32; FIG. 5(e) shows the electric potential of the word line 42 and the selector signal line 39; FIG. 6(e) shows the electric potential of the word line 42 and the selector signal line 40; FIG. 5(f) and FIG. 6(f) show the electric potential of the input signal line 34 of the sense amplifier circuit 45; FIG. 5(g) shows the electric potential of the bit line 36; FIG. 6(g) shows the electric potential of the bit line 37; FIG. 5(h) and FIG. 6(h) show the electric potential of the output line 38 of the sense amplifier circuit 45.
Address signals input into the memory device are supposed to be fixed at the time of the rising of the divided clock signal 31. The electric potential of the memory read out signal 32 is supposed to turn to the "L" logic level during a period of the "L" logic level of the divided clock signal 31.
When the divided clock signal 31 turns to the "H" logic level, an input address signal is fixed, and by decoding the fixed address signal the selector signal line 39 or 40 is selected to turn to the "H" logic level. At the same time, one of the word lines 41, 42 and 43 is selected to turn to the "H" logic level. In accordance with the selection of the word lines, a memory transistor to be read out is selected. As stated before, if the threshold value of the selected transistor is low, the electric potential of the bit line becomes the "L" logic level; if the threshold value is high, the electric potential becomes floating.
Next, the read-out operation of data stored in the memory transistor MN8 having a low threshold value will be described with reference to FIG. 4 and FIG. 5. At first, when the divided clock signal 31 turns to the "H" logic level, the electric potential of the memory read out signal line 32 turns to the "H" logic level, and the transistors MN13 and MN14 of the bit lines grounding circuit 48 are turned on. Consequently, the electric potential of the bit lines 36 and 37 turns to the "L" logic level. By decoding the address signal input into the memory device, the word line 42 is selected after an address delay time 49 and the delay time of the word line and the selector signal line 50 from the rising of the divided clock signal 31, and the gates of the memory transistors MN8 and MN11 connected to the word line 42 turns to the "H" logic level. As the result of this, the memory transistor MN8 is turned on owing to its low threshold value, and the memory transistor 11 is turned off owing to its high threshold value. Moreover, by decoding the address signal the selector signal line 39 is selected to turn to the "H" logic level similarly, and thereby the bit line 36 is connected to the input signal line 34 of the sense amplifier circuit 45.
At this time, in the sense amplifier circuit 45, since the electric potential of the memory read out signal line 32 is at the "H" logic level, the P-channel transistor MP1 is turned off. Consequently, the electric potential of the input signal line 34 of the circuit 45 takes the electric potential of the bit line 36 or the "L" logic level.
Next, when the divided clock signal 31 turns to the "L" logic level, the memory read out signal line 32 turns to the "L" logic level. Consequently, the transistors MN13 and MN14 in the bit lines grounding circuit 48 are turned off, and thereby the electric potential of the bit lines 36 and 37 tends to be determined in conformity with the states of the memory transistors MN8 and MN11, and the P-channel transistor MP1 in the sense amplifier circuit 45 is turned on at the same time to raise the electric potential of the input signal line 34 of the circuit 45. On the other hand, since the memory transistor MN8 having a low threshold value, which is selected by the word line 42 and the selector signal line 39, has been turned on at that time, the bit line 36 tends to take the ground electric potential, and thereby the electric potential of the input signal line 34 connected to the bit line 36 is limited to the electric potential not exceeding 1/2* Vcc (the threshold value of the three-state buffer 44), which potential is determined by the driving ability of the P-channel transistor MP1, the driving ability of the memory transistor MN8 and the discharge capacitance of the stray capacitance C1. As the result of that, "0" is read out on the output line 38 of the sense amplifier circuit 45.
Next, the read-out operation of data stored in the memory transistor MN11 having a high threshold value will be described with reference to FIG. 4 and FIG. 6. The operation from the turning to the "H" logic level of the divided clock signal 31 until the turning to the "L" logic level thereof is the same as that in case of FIG. 5 except for the turning to the "H" logic level of the selector signal line 40 to connect the bit line 37 to the input signal line 34 of the sense amplifier circuit 45.
When the divided clock signal 31 turns to the "L" logic level from the "H" logic level, the electric potential of the input signal line 34 of the circuit 45 rises similarly in case of FIG. 5, but since the memory transistor MN11 having a high threshold value, which is selected by the word line 42 and the selector signal line 40, has been turned off at that time, the bit line 37 takes a floating state. As the result of that, the electric potential of the input signal line 34 connected to the bit line 37 rises from the "L" logic level up to a power supply voltage Vcc through the P-channel transistor MP1, which has been turned on. Therefore, correct data, "1", is read out from the output of the three-state buffer 44 after "0" was read out transiently.
As stated before, in the conventional semiconductor memory device, information is preserved by means of memory transistors having a low threshold value and memory transistors having a high threshold value, and a word line and a selector signal line are selected by inputting an address signal and a memory read out signal, and further the information of a properly appointed memory transistor is read out as an output signal by sensing by means of the sense amplifier circuit.
In an aforementioned series of operations of reading out data from the memory device, a control circuit, not shown, of the memory device executes the generation of the divided clock signal 31 by dividing the frequency of the reference clock signal 30, the outputting of a memory read out signal, the selection of a word line by decoding an address signal, the output of a selector signal by decoding the address signal, and the like.
Since the conventional semiconductor memory device is constructed as described above, the electric potential of the input signal line 34 of the sense amplifier circuit 45 is fixed to the "L" logic level while the memory read out signal line 32 is taking the "H" logic level. Consequently, a predetermined electric potential arrival time 51 from the time when the memory read out signal line 32 is inverted from the "H" logic level to the "L" logic level up to the time when the electric potential of the input signal line 34 exceeds 1/2* Vcc, the threshold value of the three-state buffer 44, is required. Since the predetermined electric potential arrival time 51 is long, the conventional memory device has a problem that the speed for reading out the data stored in the device is slow.
On the other hand, if the memory capacity of a memory device is intended to be increased, the memory capacity is generally increased by increasing memory transistors connected to bit lines, and by increasing word lines selected by decoding address signals. But, if the number of memory transistors connected to bit lines is increased, the stray capacitance denoted by C1 and C2 in FIG. 4 is increased, and then the predetermined electric potential arrival time 51 of the input signal line 34 is elongated. Consequently, the speed of reading out data stored in the memory device becomes slow, and therefore the number of memory transistors connectable to a bit line is restricted. The conventional memory device consequently has a problem that it must enlarge the area for the layout of the circuit elements thereof because it is required to increase further sense amplifier circuits, selector circuits and bit lines grounding circuits for increasing the memory capacity of the device.
Furthermore, it can be considered to increase the frequency of the reference clock signal 30 for increasing the speed of reading out the data of the memory device. The aforementioned address delay time 49 and the delay time of the word line and the selector signal line 50 can be not fixed by the time when the divided clock signal 31 turns to the "L" logic level, and therefore they have enough time even if the frequency of the reference clock signal is increased. But, when "1" is read out, namely when the output of the sense amplifier circuit 45 is "1", since the predetermined electric potential arrival time 51 of the input signal line 34 is long, "0" is erroneously read out before the electric potential of the input signal line 34 reaches the threshold value of the three-state buffer 44 if the frequency of the reference clock signal 30 is increased. Consequently, the frequency cannot be increased. It can also be considered to shorten the predetermined electric potential arrival time 51 by improving the driving ability of the P-channel transistor MP1 instead of increasing the frequency of the. reference clock signal 30. But, if such is realized, there happens a problem that the electric potential of the input signal line 34 becomes higher than the threshold value of the three-state buffer 44 in the case where "0" is read out, and then the read out value erroneously takes "1" consequently.